Noise reduction in semiconductor devices

ABSTRACT

Some embodiments discussed relate to an integrated circuit and methods of making it, comprising a semiconductor substrate and a support layer disposed on the semiconductor substrate, wherein the support layer is doped using a noise-reducing dopant and a gate insulator disposed on the support layer, and a gate stack disposed on the gate insulator.

TECHNICAL FIELD

Embodiments described herein relate generally to semiconductor devices and more particularly, to devices having reduced noise and methods of fabricating the same.

BACKGROUND

Flicker noise is a dominant noise source in metal oxide semiconductor field-effect transistor (MOSFET) devices at low frequencies. In battery-driven circuits where signal-to-noise ratio cannot be improved at the cost of power consumption, a reduction of flicker noise is desired. Additionally, flicker noise deteriorates the performance of RF circuits having low frequency flicker noise being mixed and translated to higher frequencies in devices such as frequency mixers and voltage controlled oscillators.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a sequence of cross-sectional drawings of a partially completed semiconductor wafer showing a method of fabrication of a semiconductor wafer having a gate insulator formed using a high-k material and a support layer doped with a noise-reducing dopant, according to some embodiments of the invention.

FIG. 2 illustrates a diagram showing the potential distribution within a dielectric stack with incorporated charges, according to some embodiments of the invention.

FIG. 3 shows a flow chart illustrating a method of fabricating a semiconductor wafer having a gate insulator formed using a high-k material and a support layer doped with a noise-reducing dopant, according to some embodiments of the invention.

FIG. 4 shows a flow chart illustrating a method of fabricating a semiconductor wafer having a gate insulator formed using a high-k material and having the substrate and a support layer doped with a noise-reducing dopant, according to some embodiments of the invention.

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

In the following description, the terms “wafer” and “substrate” may be used interchangeably to refer generally to any structure on which integrated circuits are formed and also to such structured during various stages of integrated circuit fabrication. The term “substrate” is understood to include a semiconductor wafer. The term “substrate” is also used to refer to semiconductor structures during processing and may include other layers that have been fabricated thereupon. Both “wafer” and “substrate” include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art.

The term “conductor” is understood to generally include n-type and p-type semiconductors and the term “insulator” or “dielectric” is defined to include any material that is less electrically conductive than the materials referred to as “conductors.” The following detailed description is, therefore, not to be taken in a limiting sense.

Implantation of fluorine into gate stacks formed by using high-k materials does not provide adequate reduction of flicker noise in such configurations. This is especially true in the case of RF circuits that manifests the presence of switched bias noise effect which can contribute to noise reduction. Switched bias noise effect is effective only in situations were traps are present further away from the substrate-oxide interface and by this way undergo larger potential variations of the traps during switching of the gate to source voltage in a MOSFET. Due to the reduced supply voltage available in circuits used in next generation applications, the potential variation of traps in the gate insulator during switching of the gate voltage is low. This leads to a decrease in noise reduction as a result of switched bias noise effect in next generation technology applications where thinner oxides are utilized and lower supply voltages are used. Consequently, alternate methods are necessary to reduce flicker noise generated in semiconductor devices.

The following disclosure relates in general to noise reduction in switching circuits such as RF circuits, however, it may not be limited to the same. Throughout this disclosure high-K material includes a material having a relative dielectric constant that is greater than the relative dielectric constant ∈_(r) of 3.9 for silicon dioxide. Throughout this disclosure the term noise reducing dopant includes an impurity introduced in a dielectric material to quench traps in the dielectric material and at the dielectric to substrate interface that cause trapping and emitting of charges from and to the conducting channel of a MOSFET.

FIGS. 1A-1H illustrate a sequence of cross-sectional drawings of a partially completed semiconductor wafer 100 showing a method of fabrication of a semiconductor wafer having a gate insulator formed using a high-k material and a support layer doped with a noise-reducing dopant, according to some embodiments of the invention.

FIG. 1A is a cross-sectional view through a partially completed semiconductor wafer 100 including a semiconductor substrate 102 and a screening oxide layer 104 formed over semiconductor substrate 102. In some embodiments, semiconductor substrate 102 includes a silicon layer. In other embodiments, the semiconductor substrate includes a silicon layer provided over a buried oxide layer. In some embodiments, the semiconductor substrate 102 includes a fin structured silicon layer in a bulk CMOS substrate or a fin structured silicon layer over a buried oxide. In some embodiments, screening oxide 104 includes silicon dioxide. As shown in FIG. 1A, screening oxide layer 104 is grown over the silicon surface prior to a doping process. In general, screening oxide layer 104 provides protection against unintended knock-on metallic contaminants (such as iron (Fe) and Nickel (Ni)) received from an ion implanter (not shown) used to implant a pre-selected noise-reducing dopant. In some embodiments, the thickness of the screening oxide layer can range from about 1 nm to 15 nm. In a preferred embodiment, the screening oxide would be around 3 nm.

FIG. 1B is a cross-sectional view through the partially completed semiconductor wafer 100 shown in FIG. 1A illustrating the top surface of screening oxide layer 104 being exposed to an implantation process using implantation beam 105. Implantation beam 105 implants a pre-selected noise-reducing dopant into the semiconductor substrate 102.

In some embodiments, the noise-reducing dopants that may be used to dope semiconductor substrate 102 can be any one or combination of materials including Fluorine, Boron difluoride (BF₂), Boron trifluoride (BF₃), PF₃, PF₅, AsF₃, AsF₅, SbF₃, SbF₅, XeF₂, Xenon hexafluoride (XeF₆), SiF, Chlorine, Boron trichloride (BCl₃), ClF₅, SiCl₄, Deuterium, Hydrogen and their respective ions generated in a plasma including at least one fluorine, chlorine, deuterium or hydrogen atom.

FIG. 1C is a cross-sectional view through the partially completed semiconductor wafer 100 shown in FIG. 1B illustrating the semiconductor substrate 102 implanted with the pre-selected noise-reducing dopant to form a doped semiconductor substrate 106. Additionally, screening oxide layer 104 is removed by using a wet dip process. In some embodiments, the wet dip process is performed using a Hydrogen Fluoride (HF) dip. Furthermore, in some embodiments, a cleaning process is performed using ammonia hydrogen peroxide water. In some embodiments, an anneal process is performed to heal crystal damage from implant into the substrate before disposing the support layer 108. This anneal can be done before or after the following described HF vapor clean.

FIG. 1D is a cross-sectional view through the partially completed semiconductor wafer 100 shown in FIG. 1C illustrating doped semiconductor substrate 106 having a support layer 108 disposed over it. In some embodiments, the support layer 108 is formed using any one or combination of materials including silicon dioxide, nitrided silicon oxide and fluorinated silicon oxide. In some embodiments, prior to thermally growing the support layer 108, a cleaning process with HF vapor is performed to remove any kind of native oxide that may be formed on the surface of the substrate 106. This cleaning process is performed in the same chamber where the support layer is thermally grown.

In some embodiments, a high-temperature anneal, a process also called as densification is performed. This process allows for the diffusion of the noise-reducing dopants from the substrate to the substrate-support layer interface and into the support layer.

FIG. 1E is a cross-sectional view through the partially completed semiconductor wafer 100 shown in FIG. 1D illustrating doped semiconductor substrate 106 having a support layer 108 disposed over it and plasma 109 used to provide doping pre-selected noise-reducing dopants into support layer 108. In some embodiments, the noise-reducing dopants that may be used to dope support later 108 can be any one or combination of materials including Fluorine, Chlorine, ClF₅, SiCl₄, Hydrogen, Deuterium, XeF₂, Xenon hexafluoride (XeF₆) or NF₃. In some embodiments, a further anneal step may be provided to diffuse the noise reducing dopants to the substrate support layer interface.

In some embodiments, the doping dosage used for noise-reducing dopants such as Fluorine, Chlorine, Deuterium, Hydrogen is between about 1E14 atoms/cm² and about 1E16 atoms/cm². In some embodiments, the implant energy used is about 1 keV for shallow implants and about 100 keV for deep implants. In some embodiments, the implant dose and energy may have to be adjusted in situations where the noise reducing dopant used contains more than one of type of atom selected from Fluorine, Chlorine, Deuterium and Hydrogen atoms. Furthermore, as the number of noise reducing species available in a dopant mixture increases, the higher the implant energy that is required and lower the implant dose that is required, respectively.

In some embodiments, where a plasma process is used to dope the support layer, the concentration of noise reducing species in the support layer needs to reach the same amount as achieved by doping the substrate with noise reducing dopants and diffusing the noise reducing species of the dopant into the support layer through the substrate-support layer interface.

One of the advantages of introducing noise reducing dopants into substrate 106 as well as into the support layer 108 using a plasma doping process is that it provides for higher throughput during production of the semiconductor device. Additionally, a higher amount of introduced noise-reducing dopants is available in the device for noise reduction. In some embodiments, the use of materials such as BF2, BF3, PF3, AsF3, SbF3, PF5, AsF5, SbF5 to dope the substrate enhances the total amount of noise-reducing dopants available for introduction into the support layer when using a plasma process for doping the support layer.

FIG. 1F is a cross-sectional view through a partially completed semiconductor wafer 100 shown in FIG. 1E illustrating the support layer 108 after the completion of the doping process which allows for noise-reducing dopants to be impregnated into support layer 108 thereby forming a doped support layer 110. In some embodiments, a further anneal step may be provided to diffuse the noise reducing dopants inside the support layer and into the substrate-support layer interface.

FIG. 1G is a cross-sectional view through a partially completed semiconductor wafer 100 shown in FIG. 1F illustrating a gate insulator layer 112 disposed over the doped support layer 110. In some embodiments, the gate insulator layer 112 includes a material having a higher dielectric constant compared to the doped support layer 110. In some embodiments, the gate insulator layer is formed using a material having a dielectric constant higher than the support layer.

In some embodiments, the gate insulator includes any one or combination of materials having a high dielectric constant such as Al₂O₃, GD₂O₃, Yb₂O₃, Dy₂O₃, Nb₂O₅, Yb₂O₃, La₂O₃, TiO₂, Ta₂O₅, SrTiO₃, Ba_(x)Sr_(1-x)TiO₃, Zr_(x)Si_(1-x)O_(y), Hf_(x)Si_(1-x)O_(y), HfSiON, HfZrO, Al_(x)Zr_(1-x)O₂. deposited by atomic layer deposition (ALD) or metal organic chemical vapor deposition (MOCVD). In some embodiments, the gate insulator may include a nitrided silicon oxide or silicon nitride Si₃N₄.

FIG. 1H is a cross-sectional view through a partially completed semiconductor wafer 100 shown in FIG. 1G illustrating a gate stack layer 114 disposed over the gate insulator layer 112. In some embodiments, the gate insulator may include gates such as a poly silicon gate, poly silicon gate with a silicide on the top portion of the gate, a fully silicided gate and a metal gate. In some embodiments, a combination of the above mentioned gates may be used.

FIG. 2 illustrates a diagram 200 showing the potential distribution Φ(x) within a dielectric stack with incorporated charges, according to some embodiments of the invention. Additionally, diagram 200 shows in general a potential distribution Φ(x) for an NMOS device starting with a high potential at gate interface 203 to a lower potential at the substrate-oxide interface 207.

As shown in FIG. 2, a gate insulator stack 202 includes a high k material layer 204 and a support layer 206. Gate insulator stack 202 extends from the gate interface 203 at position x=0 and passes through an area of high k material layer 204 and support layer 206 made of silicon dioxide or nitrided or fluorinated silicon oxide to the interface 207 situated in between silicon dioxide layer 206 and substrate 208. In alternate embodiments, support layer 206 can include either one or a combination of materials such as nitrided silicon oxide or fluorinated silicon oxide.

The following equations provide a description for the principle of achieving noise reduction by choosing an appropriate thickness of support layer 206 and the high-k material layer 204. In the following equations, the potential in the gate insulator stack 204 comprising high-k material layer 204 and support layer 206 is calculated for the case when charges from the conducting channel of a transistor are trapped inside the gate insulator and the support layer. As a consequence of the generated potential, the trapped charges change the charge in the conducting channel of the transistor and at the gate electrode. Additionally, the trapped charge changes the mobility of the channel charges by acting as a coulomb scattering center. Both effects lead to the channel current noise of a MOSFET.

In the following equations, the effect on mobility is neglected and only the effect of trapped charge on the channel charge of the conducting channel is considered. Solving the following equations addresses the question of how different charges at different positions in the gate insulator affects the channel charge. Also, the effect of a charge in the gate insulator at the substrate to oxide interface is calculated. In the following equations the support layer includes silicon dioxide.

The following equations show the derivation of a relationship for the ratio of the thickness of the support layer to the high-k gate layer that can be used for reducing the flicker noise generated in a gate stack that is disposed on a semiconductor wafer, according to one embodiments of the invention.

Equation—1: Poisson's Equation

${\frac{\partial^{2}\varphi}{\partial x^{2}} = {- \frac{\rho (x)}{ɛ}}},{ɛ = {ɛ_{0} \cdot ɛ_{r}}}$

where,

-   -   ø=Potential     -   ρ(x)=Charge Distribution     -   ∈=Dielectric Constant     -   ∈₀=8.854E-12 A*s/(V*m)     -   ∈_(r)=relative dielectric constant

Equation—2: Electric Field is given by the following equation,

$E = {- \frac{\partial\varphi}{\partial x}}$

Equation—3: Potential Difference is given by the following equation,

${\Delta \; \varphi} = {{{\varphi (X)} - {\varphi (0)}} = {{\int_{0}^{X}{{\frac{\partial\varphi}{\partial x} \cdot 1}\ {x}}} = {{\frac{\partial\varphi}{\partial x} \cdot x}_{0}^{X}{- {\int_{0}^{X}{{x \cdot \frac{\partial^{2}\varphi}{\partial x^{2}}}\ {x}}}}}}}$

where,

-   -   X=distance from X=0 to a point X in the gate insulator,

Equation—4: Combining Equations 1, 2 and 3,

${\varphi (0)} = {{\varphi \left( T_{D} \right)} + {{E\left( T_{D} \right)} \cdot T_{D}} + {\int_{0}^{T_{D}}{{x \cdot \frac{\rho (x)}{ɛ}}\ {x}}}}$

where,

-   -   T_(D)=Total thickness of the gate insulator including the         support layer,

Equation—5: First case, where a number of channel electrons are trapped at the substrate-oxide interface 207 (in FIG. 2) and is given by the following equation:

${\varphi (0)} = {{\varphi \left( T_{D} \right)} + {{E\left( T_{D} \right)} \cdot T_{D}} - {N_{s} \cdot \frac{q}{ɛ_{0} \cdot ɛ_{{{Si}O}\; 2}} \cdot T_{D}}}$

where,

-   -   ∈_(SiO2)=dielectric constant of SiO₂ layer,     -   N_(s)=Number of trapped electrons at the substrate oxide         interface,     -   q=1.602E-19 coulombs

Equation—6: Second case, where a number of electrons N_(t)(SiO₂) are trapped in the silicon dioxide support layer 206 having distance d_(SiO2) from substrate-oxide interface as a dirac delta distribution and is given by the following equation:

${\varphi (0)} = {{\varphi \left( T_{D} \right)} + {{E\left( T_{D} \right)} \cdot T_{D}} - {{N_{t}\left( {SiO}_{2} \right)} \cdot \frac{q}{ɛ_{0} \cdot ɛ_{{SiO}\; 2}} \cdot \left( {T_{D} - d_{{SiO}\; 2}} \right)}}$

where,

-   -   N_(t)(SiO₂)=Number of trapped electrons in the silicon dioxide         layer,     -   d_(SiO2)=distance of the electrons in the silicon dioxide layer         from the substrate-oxide interface

Equation—7: Third case, where a number of electrons Nt(hk) electrons are trapped in high-k material having distance dhk from substrate-oxide interface as a dirac delta distribution and is given by the following equation:

${\varphi (0)} = {{\varphi \left( T_{D} \right)} + {{E\left( T_{D} \right)} \cdot T_{D}} - {{N_{t}({hk})} \cdot \frac{q}{ɛ_{0} \cdot ɛ_{hk}} \cdot \left( {T_{D} - d_{hk}} \right)}}$

where,

-   -   N_(t)(hk)=Number of trapped electrons in the high-k layer,     -   d_(hk)=distance of the electrons in the high-k layer from the         substrate-oxide layer,

Equation—8: From Equations 5 & 6, it can be deduced that the effective charge at the substrate-oxide interface may be given by the following equation:

${N_{s}\left( {{eff}\; {SiO}_{2}} \right)} = {{N_{t}\left( {SiO}_{2} \right)} \cdot \left( {1 - \frac{d_{{SiO}\; 2}}{T_{D}}} \right)}$

where,

-   -   N_(s)(eff SiO₂)=is the charge in the silicon dioxide layer that         is effective at the substrate-oxide interface (or that produces         the same effect as an equivalent charge at the substrate-oxide         interface),

Equation—9: From Equations 5 & 7, it can be deduced that the effective charge at the substrate-oxide interface generated by charges in the high-k layer may be given by the following equation:

${N_{s}\left( {{eff}\; {hk}} \right)} = {{N_{t}({hk})} \cdot \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \cdot \left( {1 - \frac{d_{hk}}{T_{D}}} \right)}$

Equation—10: Spectral noise power density S_(id) of drain current generated by trap distribution ρ in the oxide is given by the following equation. Here, it must be noted that the frequency contribution of traps is neglected.

${S_{id}\left( {SiO}_{2} \right)} \sim {\int_{0}^{d_{{SiO}2}}{{\left( {1 - \frac{x}{T_{D}}} \right)^{2} \cdot {\rho_{{SiO}\; 2}(x)}}\ {x}}}$

where,

S_(id)(SiO₂)=Spectral noise power density of drain current generated by trap distribution ρ in the silicon dioxide layer

Equation—11: Spectral noise power density S_(id) of drain current generated by trap distribution ρ in the high-k (neglecting frequency contribution of traps) is given by the following equation:

${S_{id}({hk})} \sim {\left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2} \cdot {\int_{d_{{SiO}\; 2}}^{d_{hk}}{{\left( {1 - \frac{x}{T_{D}}} \right)^{2} \cdot {\rho_{hk}(x)}}\ {x}}}}$

Equation—12: Total spectral noise power density of drain current is the sum of Equations 10 and 11 and is given by the following relation:

S_(id)(total)=S_(id)(SiO₂)+S_(id)(hk)

Equation—13: By solving Equation 10 for constant trap distribution in the silicon dioxide layer, it can be shown that,

${\left. {S_{id}\left( {SiO}_{2} \right)} \right.\sim{N_{t}\left( {SiO}_{2} \right)}} \cdot \left\lbrack {d_{{SiO}\; 2} - \frac{d_{{SiO}\; 2}^{2}}{T_{D}} + {\frac{1}{3} \cdot \frac{d_{{SiO}\; 2}^{3}}{T_{D}^{2}}}} \right\rbrack$

Equation—14: Solving Equation 11 for constant trap distribution in the high-k dielectric

${\left. {S_{id}({hk})} \right.\sim{N_{t}({hk})}} \cdot \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2} \cdot \left\lbrack {\left( {T_{D} - d_{{SiO}\; 2}} \right) - \frac{T_{D}^{2} - d_{{SiO}\; 2}^{2}}{T_{D}} + {\frac{1}{3} \cdot \frac{T_{D}^{3} - d_{{SiO}\; 2}^{3}}{T_{D}^{2}}}} \right\rbrack$

Equation—15: By adding Equations 13 and 14, the following equation is obtained:

${{\left. S_{id} \right.\sim{N_{t}({hk})}} \cdot \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2} \cdot \frac{1}{3} \cdot T_{D}} + {d_{{Sio}\; 2} \cdot \left( {{N_{t}\left( {SiO}_{2} \right)} - {{N_{t}({hk})} \cdot \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2}}} \right)} + {\frac{d_{{Sio}\; 2}^{2}}{T_{D}} \cdot \left( {{{N_{t}({hk})} \cdot \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2}} - {N_{t}\left( {SiO}_{2} \right)}} \right)} + {\frac{1}{3} \cdot \frac{d_{{Sio}\; 2}^{3}}{T_{D}} \cdot \left( {{N_{t}\left( {SiO}_{2} \right)} - {{N_{t}({hk})} \cdot \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2}}} \right)}$

Equation—16: The above Equation 15 can be further simplified using the relation N_(t)(SiO₂)=z*N_(t)(hk), to derive the following equation:

${{\left. S_{id} \right.\sim{N_{t}({hk})}} \cdot \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2} \cdot \frac{1}{3} \cdot T_{D}} + {{N_{t}({hk})} \cdot \left( {z - \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2}} \right) \cdot {d_{{SiO}\; 2}\left\lbrack {1 - \frac{d_{{Sio}\; 2}}{T_{D}} + {\frac{1}{3} \cdot \frac{d_{{SiO}\; 2}^{2}}{T_{D}^{2}}}} \right\rbrack}}$

where,

-   -   N_(t)(hk)=the number of effective traps in the high-k layer         which could also be due to switched bias conditions,     -   N_(t)(SiO₂)=the number of effective trapped electrons in the         SiO2 layer (support layer) due to noise reduction by using         noise-reducing dopants which could also be due to the switched         bias noise effect,     -   “z”=is the ratio between N_(t)(SiO₂) and N_(t)(hk)

In Equation 16 shown above, N_(t)(hk) can be different for switched bias conditions and constant bias conditions. Additionally, N_(t)(SiO₂), the effective traps in SiO2 due to noise reduction by noise reducing dopants may also differ due to the switched bias noise effect. Moreover, the higher potential gradient in the SiO2 layer induced by the high-k layer enhances the switched bias noise effect also for traps nearer to the substrate-oxide interface. Therefore, N_(t)(SiO₂) may also be different under switched bias and constant bias conditions.

In some embodiments, the described principle of having an increased potential gradient in moving towards the support layer substrate interface can be tailored by a dielectric with a graded dielectric constant starting with the highest dielectric constant at the gate and the lowest dielectric constant at the support layer substrate interface. In some embodiments, the graded dielectric may be fabricated by using different high-k materials having different dielectric constants. In some embodiments, a graded dielectric may be fabricated by providing fluorine doping in a lower portion of the support layer (closer to the substrate) and nitridation in an upper portion of the support layer (farther away from the substrate). In some embodiments, a multilayer structure is used to provide the graded dielectric. In some embodiments, the multilayer structure includes a a material selected from the group consisting of Al₂O₃, GD₂O₃, Yb₂O₃, Dy₂O₃, Nb₂O₅, Yb₂O₃, La₂O₃, TiO₂, Ta₂O₅, SrTiO₃, Ba_(x)Sr_(1-x)TiO₃, Zr_(x)Si_(1-x)O_(y), Hf_(x)Si_(1-x)O_(y), HfSiON, HfZrO_(x), Al_(x)Zr_(1-x)O₂, silicon nitride (Si3N4), nitrided silicon oxide, silicon dioxide and fluorinated silicon oxide.

In some embodiments, the material used closest to the gate side of the device has the highest dielectric constant and the material used nearest to the substrate of the device has the lowest dielectric constant. In some embodiments, a nitrided silicon oxide, silicon dioxide, or fluorinated silicon oxide are used at the interface of substrate and gate insulator because using other high-K would lead to unacceptable high trap densities if they are placed directly to the substrate interface.

In some embodiments, the effective number of traps depends on whether the circuit is working under a constant bias circuit or whether it is working under a switching bias condition.

Equation—17: The above Equation 16 may be simplified using the relation d_(SiO2)=y*T_(D), where y is the thickness contribution of the silicon dioxide layer. The simplified result is given by the following equation:

${{\left. S_{id} \right.\sim{N_{t}({hk})}} \cdot \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2} \cdot \frac{1}{3} \cdot T_{D}} + {{N_{t}({hk})} \cdot \left( {z - \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2}} \right) \cdot y \cdot {T_{D}\left\lbrack {1 - y + {\frac{1}{3} \cdot y^{2}}} \right\rbrack}}$

The first term in right hand side of Equation 17 is the noise contribution from high-k layer and the second term in the right hand side of Equation 17 is the noise contribution from the support layer.

For,

${\left( {z - \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2}} \right) > {zero}},$

it provides an advantage by minimizing the total noise given by Eq. 17 through reduction of the thickness of the silicon dioxide. In this case, the SiO2 layer needs to be made as small as possible while remaining at non-zero still providing the advantage of a gate insulator stack including two materials having different dielectric constants.

If

${\left( {z - \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2}} \right) < 0},$

it provides an advantage by minimizing the total noise given by Eq. 17 through the increase of the thickness contribution “z” to approach “1” but still having the high-k stack to maintain the advantages of a gate insulator stack by including two materials having different dielectric constants.

Equation—18: Solving Equation 17 for the case

$\left( {z - \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2}} \right) > 0$

and reaching 10% noise contribution from silicon dioxide layer and 90% from high-k layer, the following equation is be obtained:

${y \cdot \left\lbrack {1 - y + {\frac{1}{3} \cdot y^{2}}} \right\rbrack} = {\frac{1}{10} \cdot \left\lbrack {\frac{1}{3} \cdot \frac{1}{{\left( \frac{ɛ_{hk}}{ɛ_{{SiO}\; 2}} \right)^{2} \cdot z} - 1}} \right\rbrack}$

Furthermore, Equation 18 gives a relation of the thickness of the silicon dioxide layer with respect the support layer and allows to define a minimum oxide thickness for the case when

$\left( {z - \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2}} \right) > 0.$

Equation—19: For comparison the noise contribution with high-k dielectric only can be provided by the following equation:

${\left. S_{id} \right.\sim{N_{t}({hk})}} \cdot \frac{1}{3} \cdot T_{D}$

Equation—20: For comparison the noise contribution with oxide dielectric only (without any fluorine) can be provided by the following equation:

${\left. S_{id} \right.\sim{N_{t}\left( {SiO}_{2} \right)}} \cdot \frac{1}{3} \cdot T_{D}$

A noise reduction is achieved in the composite stack of high-k layer and silicon dioxide layer compared to pure high-k if the noise factor in Equation—17 is smaller than noise factor in Equation—19. Comparing the two equations (Equation 17 & 19), it can be shown that as a result of the introduction of the support layer, the noise of the high-k is reduced by the ratio of the square of both dielectric constants. Additionally, a noise reduction in a support layer can be achieved by the use of fluorine or other suitable noise reducing dopants implanted into the support layer.

In the case where

${\left( {z - \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2}} \right) > 0},$

the thickness of the support layer needs to be as small as possible but not zero. For the case

${\left( {z - \left( \frac{ɛ_{{SiO}\; 2}}{ɛ_{hk}} \right)^{2}} \right) < 0},$

the thickness contribution “y” of the silicon dioxide layer should approach almost one. The quantum mechanical tunneling effect provides a mechanism to explain that traps further away from the substrate-oxide interface contribute to lower frequencies compared to traps that are nearer to the substrate-oxide interface 207. In some embodiments, adjustment of the thickness “y” can be used to change the frequency behavior by frequency shaping of a particular semiconductor device.

For switching circuits, the gate stack 202 (FIG. 2), allows for an improved noise reduction capability when compared to having a gate stack with only high-k layer. This is due to the fact that the noise contribution in gate stacks with only high-k is much larger because it is difficult for the traps in the high-k layer to be quenched by a noise-reducing dopant. Consequently, gate stack 202 that has a support layer 206 (as shown in FIG. 2) included within the gate stack has an increased noise response to the switched bias noise effect in comparison to the situation where gate stacks are not provided with a support layer.

The traps in the support layer (such as silicon dioxide) which are near to the substrate-oxide interface 207 shows only small response to the switched bias noise effect because the receive only a small potential variation. But these traps in the oxide are reduced by the noise-reducing dopant. On the other hand, the high-k layer introduces a higher potential gradient which results in a larger potential variation for traps near the substrate oxide interface. By this way the noise reduction due to switched bias noise effect is also enhanced for traps near the substrate oxide interface.

In some embodiments, the silicon dioxide thickness can be varied depending on the different amounts of fluorine or chlorine that are implanted into the substrate 208. Additionally, Fluorine and chlorine has an effect on the growth rate of thermally grown oxide (both of them increase the growth rate). Consequently, in some embodiments, based on the circuit application such as a switching circuit or a non-switching circuits such e.g. a current sources, appropriate noise reduction may be provided by choosing the amount of fluorine or chlorine doping performed on the substrate.

Furthermore, fluorine has the effect of reducing the dielectric constant enhancing the ratio of dielectric constants between support layer and high-k layer.

In some embodiments, the amount of fluorine doped into the substrate may be chosen based on the amount of voltage variations seen during the operation of the circuit that is to be integrated within the semiconductor wafer. In some embodiments, different gate oxide thicknesses may be generated by using different masks. In some embodiments, different gate oxide thicknesses are provided in different areas of the semiconductor wafer. For example, by having fluorine implanted in one part of the semiconductor wafer and chlorine implanted in another portion of the semiconductor wafer varying thicknesses of gate oxides are achieved due to the different crystal growth rates for the areas doped with fluorine and chlorine or different amounts of fluorine or chlorine in different areas. The crystal growth rate for the portion of the support layer present over the area of the substrate doped with the fluorine can be adjusted differently from the crystal growth rate for the portion of the support layer present over the area of the substrate doped with the chlorine.

In some embodiments, the thickness of high-k gate insulator may be varied across the surface of the semiconductor substrate by using a masking process. This will allow for tailoring individually the noise reduction across the semiconductor substrate based on individual noise requirements of devices fabricated on the semiconductor device.

In some embodiments, different devices in different areas of the substrate may have different threshold voltage by intention to reduce noise under switched bias conditions. This provides a benefit for the switched bias noise case because the effect is dependent on the amplitude of the off-voltage in the device. Amplitude of the off-voltage is defined by the amount of gate to source voltage below the threshold voltage.

In MuGFETs the threshold voltage can be adjusted by adjusting the fin width. The larger the width the higher the threshold voltage. In planar bulk CMOS devices the threshold voltage can be adjusted by providing different backbias voltage at the substrate or the respective well in the substrate. In general the threshold voltage can be adjusted by threshold implants.

In the case of a MISFET (metal insulator semiconductor field effect transistor) device using gallium arsenide, indium gallium phosphide (InGaP) and gallium phosphide (GaP) substrates a lower noise may be achieved under switched bias conditions.

FIG. 3 is a flow chart 300 illustrating a method of fabricating a semiconductor wafer having a gate insulator formed using a high-k material and a support layer doped with a noise-reducing dopant, according to some embodiments of the invention. At 302, method 300 includes providing a semiconductor substrate 102 ready for processing.

At 304, method 300 includes forming a support layer 104 disposed over the semiconductor substrate. Forming support layer 104 includes thermally growing a support layer on the top surface of the semiconductor substrate 102. In some embodiments, the support layer 104 includes any one or combination of materials such as silicon dioxide, nitrided silicon oxide and fluorinated silicon oxide. In some embodiments, the support layer 104 is thermally grown in the same chamber where the HF vapor cleaning is done to prevent native oxide formation on the substrate.

At 306, method 300 includes doping the support layer using a noise-reducing dopant. In some embodiments, doping of the support layer 104 includes fluoridation of the support layer 104 using a plasma fluoridation process to form a doped support layer 110 (FIG. 1G). In alternate embodiments, the supporting layer is chlorinated using a plasma chlorination process. In some embodiments, plasma fluoridation and chlorination of the support layer may be done using chemical materials such as Fluorine (F₂), Chlorine (Cl₂), ClF₅, XeF2, XeF6, SiCl4, NF3 and their respective ions that are generated in a plasma. In some embodiments, plasma fluoridation, chlorination, deuterium or hydrogen incorporation is performed using noble gases that are added with fluorine, chlorine, deuterium or hydrogen containing gases in the plasma chamber.

At 308, method 300 includes forming a gate insulator 112 disposed over the doped support layer 110. In some embodiments, the upper portion of the support layer may be nitrided using a plasma nitridation process. The plasma nitridation process allows for increasing the dielectric constant of the upper portion of the support layer and consequently the combined dielectric of the high-k gate insulator and the support layer remains in the high-k region.

In some embodiments, different support layer thicknesses may be provided by doping different amounts of fluorine or chlorine into the substrate. Doping different amounts of fluorine or chlorine allows for adjusting for noise related to various devices that are fabricated on the semiconductor wafer.

In some embodiments, a first thickness of the support layer is provided for circuits that operate under a constant bias condition and a second thickness if provided for circuits that operate under a switched bias condition. Examples of circuits operating under a constant bias condition includes current mirrors and similar circuits. Examples of circuits operating under a switched bias condition includes frequency mixers, voltage controlled oscillators, etc.

At 310, method 300 includes forming a gate stack 114 disposed over the gate insulator 112.

FIG. 4 shows a flow chart 400 illustrating a method of fabricating a semiconductor wafer having a gate insulator formed using a high-k material and having the substrate and a support layer doped with a noise-reducing dopant, according to some embodiments of the invention.

At 402, method 400 includes providing a semiconductor substrate 102 having a screening oxide layer 104 over substrate 102.

At 404, method 400 includes implanting the semiconductor substrate 102 with a noise reducing dopant by ion implantation. In some embodiments, the materials used for noise reducing dopant includes anyone or combination of materials and their respective ions such as Fluorine, Boron difluoride (BF₂), Boron trifluoride (BF₃), PF₃, PF₅, AsF₃, AsF₅, SbF₃, SbF₅, XeF₂, Xenon hexafluoride (XeF₆), SiF, Chlorine, Boron trichloride (BCl₃), CIF₅, SiCl₄, Deuterium, Hydrogen and their respective ions generated in a plasma including at least one fluorine, chlorine, deuterium or hydrogen atom.

At 406, method 400 includes removing the screening oxide layer 104 using a wet hydrogen fluoride (HF) dip.

At 408, method 400 includes cleaning the top surface of the semiconductor substrate 102 using ammonium hydrogen peroxide water.

At 410, method 400 includes annealing semiconductor substrate 102 and removing any native oxide formed on the surface of substrate 102 with HF vapor. In some embodiments, annealing substrate 102 includes maintaining the semiconductor wafer at a temperature between about 950° C. and about 1200° C. for a time period between about 1 second and about 60 seconds.

At 412, method 400 includes thermally growing a support layer 108 on the top surface of the doped semiconductor substrate 106 (FIG. 1D). In some embodiments, support layer 108 includes any one or combination of materials such as silicon dioxide, nitrided silicon oxide and fluorinated silicon oxide. In some embodiments, the support layer is thermally grown in the same chamber where the HF vapor cleaning is done to prevent native oxide formation on the substrate.

At 414, method 400 includes doping the support layer 108 to form doped support layer 110 (FIG. 1F). In some embodiments, support layer 108 is fluorinated using a plasma fluoridation process. In alternate embodiments, support layer 108 is chlorinated using a plasma chlorination process. In some embodiments, plasma fluoridation and chlorination of support layer 108 may be performed using chemical materials such as Fluorine (F₂), Chlorine (Cl₂), CIF₅, XeF2, XeF6, SiCl4, NF3 and their respective ions that are generated in a plasma. In some embodiments, plasma fluoridation, chlorination, deuterium or hydrogen incorporation is performed using noble gases that are added with fluorine, chlorine, deuterium or hydrogen containing gases in the plasma chamber.

In some embodiments, the upper portion of support layer 108 may be nitrided using a plasma nitridation process. The plasma nitridation process allows for increasing the dielectric constant of the upper portion of support layer 108 and consequently the combined dielectric of the high-k gate insulator 112 (FIG. 1G) and the doped support layer 110 remains in the high-k region.

In some embodiments, different support layer thicknesses may be provided by doping different amounts of fluorine or chlorine into the substrate. Doping different amounts of fluorine or chlorine allows for adjusting for noise related to various devices that are fabricated on the semiconductor wafer.

In some embodiments, a first thickness of the support layer 110 is provided for circuits that operate under a constant bias condition and a second thickness if provided for circuits that operate under a switched bias condition. Examples of circuits operating under a constant bias condition includes current mirrors and similar circuits. Examples of circuits operating under a switched bias condition includes frequency mixers, voltage controlled oscillators, etc.

At 414, method 400 includes forming a gate insulator layer 112 disposed on the support layer. In some embodiments, gate insulator layer 112 has a dielectric constant greater than support layer 110. In some embodiments, the gate insulator layer 112 includes any one or combination of the materials and their respective ions such as Al₂O₃, GD₂O₃, Yb₂O₃, Dy₂O₃, Nb₂O₅, Yb₂O₃, La₂O₃, TiO₂, Ta₂O₅, SrTiO₃, Ba_(x)Sr_(1-x)TiO₃, Zr_(x)Si_(1-x)O_(y), Hf_(x)Si_(1-x)O_(y), HfSiON, HfZrO_(x), Al_(x)Zr_(1-x)O₂, nitrided silicon oxide or silicon nitride Si3N4.

In some embodiments, the gate insulator material is deposited using a atomic layer deposition process. In alternate embodiments, the gate insulator material is deposited using a metal organic chemical vapor deposition process.

In some embodiments, the thickness of high-k gate insulator may be varied across the surface of the semiconductor substrate by using a masking process. This will allow for tailoring individually the noise reduction across the semiconductor substrate based on individual noise requirements of devices fabricated on the semiconductor device.

In some embodiments, a nitrided silicon oxide is formed as a high-k portion of the support layer. In some embodiments, the nitridation of the silicon dioxide is performed to a different depth.

At 416, method 400 includes forming a gate stack 114 disposed on the gate insulator layer 112.

In some embodiments, the integrated circuit fabricated according the method described above includes at least one of a planar CMOS FET, a fin FET containing two conducting planes (MOSFET channels) and a multi-gate FET containing 3, 4 or 5 conducting planes.

It should be noted that the methods described herein do not have to be executed in the order described, or in any particular order, unless it is otherwise specified that a particular order is required. Moreover, unless otherwise specified, various activities described with respect to the methods identified herein can be executed in repetitive, simultaneous, serial, or parallel fashion.

The accompanying drawings that form a part hereof show by way of illustration, and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.

Such embodiments of the inventive subject matter may be referred to herein, individually and/or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. In the previous discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including” , but not limited to . . . ”.

The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72 (b), requiring the abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. 

1. An integrated circuit, comprising: a semiconductor substrate; a support layer disposed on the semiconductor substrate, wherein the support layer is doped using a noise-reducing dopant; a gate insulator disposed on the support layer; and a gate stack disposed on the gate insulator.
 2. The integrated circuit in claim 1, wherein the gate insulator includes a material with dielectric constant greater than the dielectric constant of the support layer.
 3. The integrated circuit of claim 2, wherein the noise-reducing dopant includes a material selected from the group consisting of Fluorine, Chlorine, ClF₅, SiCl₄, Hydrogen, Deuterium, XeF2, Xenon hexafluoride XeF₆ and NF3.
 4. The integrated circuit of claim 2, wherein the support layer includes a material selected from the group consisting of silicon dioxide, nitrided silicon oxide and fluorinated silicon oxide.
 5. The integrated circuit of claim 2, wherein the support layer includes a first portion having a first thickness and a second portion having a second thickness, wherein the first portion is configured to support a first circuit adapted to operate under a constant bias condition and the second portion is configured to support a second circuit adapted to operate under a switching bias condition.
 6. The integrated circuit of claim 2, wherein the gate insulator includes a layer having first thickness at a first portion of the gate insulator and a second thickness at a second portion of the gate insulator.
 7. The integrated circuit of claim 2, wherein the gate insulator includes a material selected from the group consisting of Al₂O₃, GD₂O₃, Yb₂O₃, Dy₂O₃, Nb₂O₅, Yb₂O₃, La₂O₃, TiO₂, Ta₂O₅, SrTiO₃, Ba_(x)Sr_(1-x), TiO₃, Zr_(x)Si_(1-x)O_(y), HfSiON, HfZrO_(x), Al_(x)Zr_(1-x)O₂, nitrided silicon oxide and silicon nitride Si₃N4.
 8. The integrated circuit of claim 2, wherein the gate stack a material selected from the group consisting of a poly silicon gate, a fully silicided gate and a metal gate.
 9. The integrated circuit of claim 2, wherein the substrate is implanted with a second noise-reducing dopant.
 10. The integrated circuit of claim 9, wherein the second noise reducing dopant includes a material selected from the group consisting of Fluorine, Boron difluoride BF2, Boron trifluoride BF3, PF₃, PF₅, AsF₃, AsF₅, SbF₃, SbF₅, Chlorine, Boron trichloride BCl3, ClF₅, SiF, SiCl₄, Hydrogen, Deuterium, XeF2, and Xenon hexafluoride XeF6.
 11. The integrated circuit of claim 1, further comprising: at least one of a planar CMOS FET, a fin FET having two conducting channels and a multi-gate FET having more than two conducting channels.
 12. A method of fabricating an integrated circuit, comprising: providing a semiconductor substrate; forming a support layer disposed over the semiconductor wafer; doping the support layer using a noise-reducing dopant; forming a gate insulator disposed over the support layer, wherein the dielectric constant of the gate insulator is greater than the dielectric constant of the support layer; and forming a gate stack disposed over the gate insulator.
 13. The method of claim 12 includes determining a thickness of the support layer adapted to minimize the total flicker noise contribution by the gate insulator and the support layer, wherein the ratio is determined by minimizing the equation for the spectral noise power density S_(id): $S_{id} = {{K_{1} \cdot \left\{ {{N_{t}({hk})} \cdot \left( \frac{ɛ_{Support}}{ɛ_{hk}} \right)^{2} \cdot \frac{1}{3} \cdot T_{D}} \right\}} + {K_{2} \cdot \left\{ {{N_{t}({hk})} \cdot \left( {z - \left( \frac{ɛ_{Support}}{ɛ_{hk}} \right)^{2}} \right) \cdot y \cdot {T_{D}\left\lbrack {1 - y + {\frac{1}{3} \cdot y^{2}}} \right\rbrack}} \right\}}}$ where, K1=is a constant based on the frequency dependence of traps located in the high-k. K2=is a constant based on the frequency dependence of traps located in the support layer. N_(t)(hk)=the number of effective traps in the high-k layer. “z” =ratio between N_(t)(Support) and N_(t)(hk), where N_(t)(Support) is the number of effective trapped electrons in the SiO2 layer (support layer) due to noise reduction by using noise-reducing dopants, T_(D) y=ratio of the thickness of the gate support layer and the thickness of dielectric T_(D)
 14. The method of claim 12, wherein forming the support layer includes forming a first portion of the support layer having a first thickness including a first circuit operating under a constant bias condition and forming a second portion of the support layer having a second thickness including a second circuit operating under a switched bias condition.
 15. The method of claim 12, further comprising: removing an oxide layer covering the semiconductor substrate using a wet Hydrogen Fluoride (HF) dip process prior to forming the support layer.
 16. The method of claim 15, wherein removing the oxide layer includes cleaning the semiconductor substrate after the HF dip using a cleaning agent including ammonia hydrogen peroxide water.
 17. The method of claim 16, wherein removing the native oxide layer further comprises cleaning the semiconductor substrate using a cleaning agent including hydrogen fluoride (HF) vapor.
 18. The method of claim 12, wherein forming the support layer disposed over the semiconductor substrate includes forming the support layer by thermally growing silicon dioxide.
 19. The method of claim 14, wherein forming the first portion of the support layer includes thermally growing over the substrate layer having a first portion doped with a first doping agent, and forming the second portion of the support layer includes thermally growing over the substrate layer having a second portion doped with a second doping agent.
 20. The method of claim 12, wherein forming the gate insulator disposed over the support layer includes forming a first portion having a first thickness and forming a second portion having a second thickness.
 21. The method of claim 18, wherein forming the support layer disposed over the semiconductor substrate includes forming a nitrided silicon oxide layer within the support layer.
 22. The method of claim 12, wherein doping the support layer using a noise-reducing dopant includes doping the support layer using a material selected from the group consisting of Fluorine, Chlorine, ClF₅, SiCl₄, Hydrogen, Deuterium, XeF2, Xenon hexafluoride XeF6, and NF3.
 23. The method of claim 12, wherein forming the gate insulator disposed over the support layer includes forming the gate insulator using a material selected from the group consisting of Al₂O₃, GD₂O₃, Yb₂O₃, Dy₂O₃, Nb₂O₅, Yb₂O₃, La₂O₃, TiO₂, Ta₂O₅, SrTiO₃, Ba_(x)Sr_(1-x)TiO₃, Zr_(x)Si_(1-x)O_(y), Hf_(x)Si_(1-x)O_(y), HfSiON, HfZrO_(x), Al_(x)Zr_(1-x)O₂, nitrided silicon oxide and silicon nitride (Si3N4).
 24. The method of claim 12, wherein forming the gate stack disposed over the gate insulator layer includes forming the gate stack including at least one of a poly silicon gate, a fully silicided gate and a metal gate.
 25. The method of claim 21, wherein the nitrided silicon oxide layer is formed by a plasma nitridation process.
 26. The method of claim 12, wherein providing the gate stack disposed over the support layer includes providing the gate stack including at least one of a poly silicon gate, a fully silicided gate and a metal gate.
 27. The method of claim 12, further comprising: implanting the semiconductor substrate using a second noise-reducing dopant.
 28. The method of claim 12, implanting the semiconductor substrate using the second noise reducing dopant includes implanting the semiconductor substrate with a material selected from the group consisting of Fluorine, Boron difluoride BF2, Boron trifluoride BF3, PF₃, PF₅, AsF₃, AsF₅, SbF₃, SbF₅, Chlorine, Boron trichloride BCl3, CIF₅, SiF, SiCl₄, Hydrogen, Deuterium XeF2, and Xenon hexafluoride XeF6.
 29. The method of claim 12, wherein forming the support layer further comprises annealing the semiconductor substrate to treat crystal damage and removing a native oxide by HF vapor cleaning in a chamber followed by thermally growing the support layer in the chamber.
 30. A method of fabricating an integrated circuit, comprising: providing a semiconductor substrate having a first portion and second portion, wherein the first portion is implanted with a first noise-reducing dopant and the second portion is implanted with a second noise reducing dopant; thermally growing a support layer disposed over the first portion and the second portion of the semiconductor substrate; doping the support layer using a third noise-reducing dopant; forming a gate insulator disposed over the support layer, wherein the dielectric constant of the gate insulator is greater than the dielectric constant of the support layer; and forming a gate stack disposed over the gate insulator.
 31. The method of claim 30, wherein forming the gate insulator disposed over the support layer includes forming a first portion having a first thickness and forming a second portion having a second thickness.
 32. An integrated circuit, comprising: a semiconductor substrate; a gate insulator supported by the semiconductor substrate, the gate insulator including a dielectric layer with a graded dielectric constant; and a gate stack disposed on the gate insulator.
 33. The integrated circuit of claim 32, wherein the dielectric layer is adapted to reduce flicker noise in the integrated circuit under switched bias condition.
 34. The integrated circuit of claim 32, wherein the dielectric constant decreases from the gate to the substrate.
 35. The integrated circuit of claim 34, comprising: a support layer disposed on the semiconductor substrate doped with a noise-reducing dopant.
 36. The integrated circuit of claim 34, wherein the dielectric layer is doped with a noise-reducing dopant.
 37. The integrated circuit of claim 34, wherein the dielectric layer includes a dielectric layer having a continuously varying dielectric constant.
 38. The integrated circuit of claim 34, wherein the dielectric layer includes a plurality of dielectric layers stacked between the substrate and the gate stack. 